Data scrambler

ABSTRACT

A data scrambler receives a parallel array of input bits. An array of previously scrambled output bits are stored from a previous clock period. The array of previously scrambled output bits are applied to the parallel array of input bits during a same current clock period to generate a current array of scrambled output bits.

BACKGROUND

[0001]FIG. 1 shows a traditional scrambler circuit 12 and a traditionalde-scrambler circuit 14. The scrambler circuit 12 scrambles a serialdata input stream 16 bit by bit. A first input bit is input into anExclusive OR (XOR) gate 18. The 39^(th) polynomial X(39) and 58^(th)polynomial X(58) are XORed together by a XOR gate 20. The result fromXOR 20 is XORed with the input bit 16 by XOR gate 18. The scrambledoutput is fed into a first D-flip-flop 22. Each clock cycle another bitis serially fed into the XOR gate 18 and the output sequenced throughthe series of D-flip-flops 22.

[0002] The de-scrambler circuit 14 works in a similar manner. Thescrambled serial data stream 24 is sequenced bit by bit through a seriesof D-flip-flops 26. The 39^(th) polynomial X(39) is XOR'd with the58^(th) polynomial X(58) by XOR gate 28. The result is XOR'd with thescrambled data bit 24 by XOR gate 30. The output from the XOR gate 30 isthe de-scrambled serial bit stream that was originally fed intoscrambler circuit 12.

[0003] This traditional serial scrambler/de-scrambler circuitry is tooslow and complex for high speed data traffic. The present inventionaddresses this and other problems associated with the prior art.

SUMMARY OF THE INVENTION

[0004] A data scrambler receives a parallel array of input bits. Anarray of previously scrambled output bits are stored from a previousclock period. The array of previously scrambled output bits are appliedto the parallel array of input bits to generate an array of scrambledoutput bits during the same clock period.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1 is a schematic diagram of a prior art serial data scramblerand de-scrambler.

[0006]FIG. 2 is a block diagram of a parallel scrambler circuit.

[0007]FIG. 3 is a list of new seed values stored by the parallelscramble circuit.

[0008]FIG. 4 is a list of how the new seeds are applied to an input dataarray.

[0009]FIG. 5 shows an example of how the new seeds are determined for aparticular input bit.

[0010]FIG. 6 shows another example of how the new seeds are determinedfor a different input bit.

[0011]FIG. 7 is a block diagram of a parallel de-scrambler circuit.

[0012]FIG. 8 is a block diagram showing how the parallel scrambler andde-scrambler circuits are used in a high speed network processor.

DETAILED DESCRIPTION

[0013]FIG. 2 shows a N-Bit parallel data scrambler 40. The scrambler 40generates an array of new seed values that are used to generate an arrayof scramble polynomials that are applied in parallel to an array ofinput bits. This allows an array of scrambled bits to be generatedduring the same clock period. In the example below, the scramblepolynomial 1+X(39)+X(58) is applied to a 64 bit array of input bits.However, any polynomial values can be used and applied to any bit lengtharray of input bits using the scramble technique described below.

[0014] The parallel scrambler 40 reduces the complexity of previousscrambler designs and provides higher scrambling throughput simply byexpanding the width of a data bus. The parallel scrambler 40 can be usedin any data processing application and in one application is used forscrambling 10 gigabit network traffic.

[0015] Referring to FIG. 2, the N-bit parallel data scrambler 40includes an input data register 42, scrambling logic 46, a new seedregister 48, and an output data register 50. Any of these functionalblocks may be implemented separately or together in software using aprogrammable processor device or using discrete logic devices.

[0016] After power up and enabling, the seed register 48 is loaded witha set of programmable seeds. An array of data from a parallel input datastream 41 is loaded into input data register 42 at the rising edge of afirst clock period generated by clock 47. During a second clock period,the scrambler circuit 46 scrambles every bit from the parallel data bus41 with the scramble polynomial 1+X(39)+X(58) using the pre-loaded newseed values 43 stored in seed register 48.

[0017] At the rising edge of the second clock period, the scrambledparallel data stream from scrambler circuit 46 is loaded into the outputdata register 50. At the same time, a new set of seed values 45 areloaded into the new seed register 48. A next array of bits from theparallel input data stream 41 are also loaded into the input dataregister 42. This process then repeats. The scrambling scheme can beeasily adapted for any bit length.

[0018]FIG. 3 shows the scrambled output values used for the new seedvalues 45 (FIG. 2). For example, the sixth scrambled output bit Dout(6)in a current clock period is loaded into the seed register 48 (FIG. 2)as the seed value NS′(57). The new seed value NS′(57) is used during thenext clock period. The thirty ninth scrambled output bit Dout(39)generated during the current clock period is loaded into the seedregister 48 as the next seed value NS′(24). The new seed valuesNS′(57)−NS′(0) are then used for scrambling a next array of input bitsthat are output from input data register 42 (FIG. 2) during a next clockperiod. The relationship between the new seed values and the scrambledoutput values for a parallel data bus width of N=64 is summarized below.TABLE #1 NS[57:0] = Dout[M:N]; where, M = N − 58, and N = 64.

[0019]FIG. 4 shows how the different input bits are scrambled using thenew seed bit values NS(57)−NS(0) from the new seed register 48 (FIG. 2).For a scramble polynomial of 1+X(39)+X(58), the scramble polynomialscheme is shown below in table #2. The symbol “^ ” refers to anexclusive OR function. TABLE #2 Parallel Data Output Bits[0:38]:Dout[0:38] = NS[38:0] ^ NS[57:19] ^ Din[0:38]. Parallel Data OutputBits[39:57]: Dout[39:57] = NS[18:0] ^ NS[38:20] ^ NS[57:39] ^ Din[0:18]^ Din[39:57]. Parallel Data Output Bits[58:N] (58 < N < 96): Dout[58:N]= NS[19:14] ^ NS[57:52] ^ Din[0:5] ^ Din[19:24] ^ Din[58:63].

[0020] Referring to FIG. 4, a first scrambled output bit Dout(0) for acurrent clock period is generated by XORing new seed values NS(38), newseed value NS(57), and input bit value Din(0). The next scrambled outputbit Dout(1) is generated by XORing new seed NS(37), new seed NS(56), andinput bit value Din(1). The scrambling scheme changes for output bitsDout(39)−Dout(57). For example, Dout(45) is generated by XORing new seedNS (12), NS(32) and NS(51) and input bit values Din(6) and Din(45). Athird scheme shown in FIG. 4 is used for scrambling output bitsDout(58)−Dout(63).

[0021]FIG. 5 further illustrates how the parallel scrambler circuitoperates. The bits 62 represent the scrambled output bits generated fora current clock period t=t. The bits 64 represent the scrambled outputbits generated for a previous clock period t=t−1. An output bit Dout(19)is identified as item 60 in FIG. 5. The polynomials X(39) and X(58) aredetermined for generating a scrambled output bit Dout(19) for input bitDin(19). For Dout(19), the polynomial X(39) is determined by countingback 39 previous scrambled output bit locations. For example, Dout(18)is one bit location, Dout(17) is a second bit location, etc.

[0022] After counting back 19 previous output bit locations to Dout(0),the scrambled output bits 64 for the previous clock period time t=t−1are used. For example, the 20^(th) previous scrambled output bitlocation for Dout(19) is scrambled output bit Dout(63) from bits 64generated during the previous clock period. Similarly, the 21^(st)previous scrambled output bit is Dout(62) from the previous clockperiod, output bits 64. The 39^(th) polynomial X(39) for Dout(19) isidentified as Dout(44) from the previous clock period output bits 64.Counting back 58 positions from Dout(19), the 58^(th) polynomial X(58)is identified as scrambled output bit Dout(25) from the previous clockcycle output bits 64.

[0023] Referring back to FIGS. 3 and 4, Dout(44) from a current clockperiod t=t is stored in new seed location NS′(19) and Dout(25) is storedin new seed location NS′(38). Thus, the scrambler value used forapplying the polynomial 1+X(39)+X(58) to generate Dout(19) is NS(19)^NS(38)^ Din(19). Accordingly, the register location NS′(19) in new seedregister 48 (FIG. 2) is loaded by the scrambler circuit 46 with thevalue Dout(44) and the new seed location NS′(38) in the new seedregister 48 is loaded by the scrambler circuit 46 with the valueDout(25). The scrambler circuit 46 then XORs NS(19)^ NS(38)^ Din(19) togenerate the scramble polynomial 1+X(39)+X(58) for Dout(19).

[0024]FIG. 6 shows an example of how the scrambled output value isgenerated for output bit Dout(50) identified as item 56. The scrambledvalue for Dout(50) is derived using the relationship NS(7)^ NS(27)^NS(46)^ Din(11)^ Din(50). Bits 66 represent the scrambled output bitsfor a current clock period, and bits 68 represent the scrambled outputbits for a previous clock period. The 39^(th) polynomial X(39) forDout(50) is the scrambled output bit Dout(11) identified as item 70 inFIG. 6. The scrambled value Dout(11) is derived from the equationNS(27)^ NS(46)^ Din(11) (FIG. 4). The 58^(th) polynomial X(58) forDout(50) is Dout (56) and is identified as item 71 from bits 68. Thevalue of Dout(56) is loaded into new seed register NS(7).

[0025] This procedure is applied to each bit in the array of input bitsfor a current clock period. Any scramble polynomial can be applied toany length array of parallel bits to generate an array of scrambledoutput bits during the same clock period.

[0026] Referring to FIG. 7, a N-bit parallel data de-scrambler 79 issimilar to the scrambler shown in FIG. 2. The de-scrambler 79 includesan input data register 82, scrambling logic 90, new seed register 86,and an output data register 94. The scrambled parallel input data stream80 is loaded into the input data register 82 at the rising edge of acurrent clock period generated by the clock circuit 96. During a nextclock period, the de-scrambling circuit 90 de-scrambles every bit of thescrambled parallel data bus 80 with the de-scrambling polynomial1+X(39)+X(58) using the parallel input data from data register 82 andthe pre-loaded new seed values pre-loaded into the new seed register 86during a previous clock period.

[0027] At the rising edge of the current clock period, the de-scrambledparallel data stream from de-scrambler circuit 90 is loaded into theoutput data register 94. At the same time, a new set of seed values 92are loaded from the de-scrambler 90 into the new seed register 86 andanother new set of parallel input data 80 is loaded into the input dataregister 82.

[0028]FIG. 8 shows one example of how the parallel scrambler andde-scrambler circuits are implemented in a network processing device 99.In one example, the network processing device 99 is a high speed gigabitrouter, however, it should be understood that the scrambler scheme canbe used in any data processing device. The network processing device 99includes packet processing circuitry 102 that is coupled to a network100. The network 100 can be any local or wide area network, such as aLocal Area Network (LAN), Wide Area Network (WAN), Metropolitan AreaNetwork (MAN), etc.

[0029] The packet processing circuitry 102 includes an ingress networkprocessor 104 that receives network packets from network 100. Ade-scrambler circuit 106 makes up part of the ingress network processor104 and de-scrambles packets as described above in FIG. 7. Thede-scrambled bits from the network packets are sent to an ingress buffermanager 112 that includes a scrambler circuit 114 as shown above in FIG.2. The scrambler circuit 114 scrambles the array of packet bits beforethey are output by the ingress buffer manager 112 to a switch fabric120.

[0030] Controllers 122 determine the egress ports where the switchfabric 120 transfers the scrambled bits. The egress buffer manager 116includes a de-scrambler circuit 118 that de-scrambles arrays of thepacket bits scrambled by scrambler 114. A scrambler circuit 110 in theegress network processor 108 then scrambles the array of packet bitsbefore being output on network 100.

[0031] The system described above can use dedicated processor systems,micro controllers, programmable logic devices, or microprocessors thatperform some or all of the scrambling and de-scrambling operations. Someof the operations described above may be implemented in software andother operations may be implemented in hardware.

[0032] For the sake of convenience, the operations are described asvarious interconnected functional blocks or distinct software modules.This is not necessary, however, and there may be cases where thesefunctional blocks or modules are equivalently aggregated into a singlelogic device, program or operation with unclear boundaries. In anyevent, the functional blocks and software modules or described featurescan be implemented by themselves, or in combination with otheroperations in either hardware or software.

[0033] Having described and illustrated the principles of the inventionin a preferred embodiment thereof, it should be apparent that theinvention may be modified in arrangement and detail without departingfrom such principles. Claim is made to all modifications and variationcoming within the spirit and scope of the following claims.

1. A data scrambler, comprising: a scrambler device configured toscramble a parallel array of input bits into an array of scrambledoutput bits all during a same current clock period.
 2. A data scrambleraccording to claim 1 including a new seed register for storing thescrambled output bits from a previous clock period and supplying thescrambled output bits to the scrambler device for applying to theparallel array of input bits during the current clock period.
 3. A datascrambler according to claim 1 wherein the scrambler device generates anarray of polynomial values for applying to the parallel array of inputbits by feeding back an array of scrambled output bits generated duringa previous clock period.
 4. A data scrambler according to claim 3including a seed register for storing the array of scrambled outputbits.
 5. A data scrambler according to claim 3 wherein the scramblerdevice selects the scrambled output bits for applying to each one of theinput bits according to a polynomial value, a bit length for theparallel array of input bits, and a position of the input bits in theparallel array.
 6. A data scrambler according to claim 1 wherein a1+X(39)+X(58) scramble polynomial is applied to each bit of the parallelarray of input bits according to the following: Dout[0:38]=NS[38:0]^NS[57:19]^ Din[0:38]; Dout[39:57]=NS[18:0]^ NS[38:20]^ NS[57:39]^Din[0:18]^ Din[39:57]; and Dout[58:N]=NS[19:14]^ NS[57:52]^ Din[0:5]^Din[19:24]^ Din[58:63]; where, Dout are the scrambled output bitsgenerated during the current clock period, Din are the input bits,NS[57:0]=Dout′[M:N], M=N−58, N=64, and Dout′ are the scrambled outputbits generated during a previous clock period.
 7. A data scrambleraccording to claim 2 including an input data register configured tooutput the parallel array of input bits to the scrambler device and anoutput data register for receiving the array of scrambled output bitsfrom the scrambler device.
 8. A data scrambler according to claim 1wherein an output of the scrambler device is coupled to both the outputdata register and the new seed register and an output of the new seedregister is coupled to the scramble device.
 9. A data scrambleraccording to claim 1 including an ingress buffer manager that uses thescrambler device to scramble the array of input bits from networkpackets transferred over a switch fabric.
 10. A data scrambler accordingto claim 1 including an egress network processor that uses the scramblerdevice to scramble the array of input bits from network packets sentover a network.
 11. A method for scrambling data, comprising: receivinga parallel array of input bits; storing an array of previously scrambledoutput bits from a previous clock period; and applying the array ofpreviously scrambled output bits to the parallel array of input bitsduring a same current clock period to generate a current array ofscrambled output bits.
 12. A method according to claim 11 includingstoring the previous scrambled output bits from the previous clockperiod as new seed values for applying scramble polynomials to each ofthe parallel array of input bits during the same current clock period.13. A method according to claim 12 including selecting the new seedsvalues according to scramble polynomial values, a bit length of theparallel array of input bits, and a position of the individual bits inthe parallel array of input bits.
 14. A method according to claim 11including using the stored array of previously scrambled output bits toapply a 1+X(39)+X(58) scramble polynomial to each one of the parallelarray of input bits during the same current clock period.
 15. A methodaccording to claim 11 including: receiving a parallel array of scrambledinput bits; storing an array of previously de-scrambled output bitsde-scrambled during a previous clock period; and applying the array ofpreviously de-scrambled output bits to the parallel array of scrambledinput bits during a same current clock period to generate a currentarray of de-scrambled output bits.
 16. A method according to claim 15including storing the current array of de-scrambled output bits as newseed values for applying to a next parallel array of scrambled inputbits during a next clock period.
 17. A method according to claim 11including: scrambling the parallel array of input bits for networkpackets in a network router; transferring the network packets over aswitch fabric in the network router; and de-scrambling the scrambledparallel array of input bits received over the switch fabric.
 18. Amethod according to claim 11 including: de-scrambling a parallel arrayof scrambled packet bits received over a network; and scramblingparallel arrays of de-scrambled packet bits during the same clock periodbefore sending the packet bits over the network.
 19. A networkprocessing device, comprising: an ingress circuit configured to processpackets received over a network; an egress circuit configured to processpackets for sending over the network; a switch fabric for transferringpackets between the ingress circuit and the egress circuit; and ascrambler circuit configured to scramble a parallel array of packet bitsinto an array of scrambled output bits during a same current clockperiod.
 20. A network processing device according to claim 19 includinga new seed register for storing an array of scrambled output bits from aprevious clock period and supplying the array of scrambled output bitsto the scrambler circuit for applying to the parallel array of packetbits during the current clock period.
 21. A network processing deviceaccording to claim 20 including a first scrambler circuit and new seedregister located in the ingress circuit for scrambling the array ofpacket bits before being transferred over the switch fabric and a secondscrambler circuit and new seed register located in the egress circuitfor scrambling the array of packet bits before being transferred overthe network.
 22. A network processing device according to claim 20including a de-scrambler circuit configured to de-scramble the array ofscrambled packet bits into an array of de-scrambled packet bits during asame current clock period.
 23. A network processing device according toclaim 22 including a de-scrambler new seed register for storing an arrayof de-scrambled packet bits from a previous clock period and supplyingthe array of de-scrambled output bits to the de-scrambler circuit forapplying to the scrambled packet bits during the current clock period.24. A network processing device according to claim 23 including a firstde-scrambler circuit and de-scrambler new seed register located in theingress circuit for de-scrambling arrays of packet bits after beingreceived from the network and a second de-scrambler circuit and new seedregister located in the egress circuit for de-scrambling arrays ofscrambled packet bits received over the switch fabric.